Comparing Interconnection Models in an On-Chip Reconfigurable Multiprocessor

The increasing complexity of present SoCs demands new, scalable, reusable, parallel interconnection models for their cores. This paper presents a comparison study made in an on chip reconfigurable multiprocessor, the X4CP32, on its interconnection. Three models were proposed, a bus system, a SoC using FIFO buffering, and a SoC using SAFC buffering. All the models were described in SystemC and simulated. Results show a great difference between the NoCs’ and the bus system’s performance.